1. Field of the Invention
The present invention relates generally to a bus system and an information processing system including the bus system. More particularly, the invention relates to a bus system and an information processing system using control command line in common between a plurality of buses having different bit widths and having a data conversion unit performing data transfer between buses with conversion of bit widths.
2. Description of the Related Art
In recent years, attention has been attracted to a method for shortening a design period of LSI and reducing development cost of LSI by connecting circuit blocks developed in the past as intellectual property (IP) or design resource core.
Since each of such circuit blocks is frequently developed independently of each other, there should present difference in bus width and/or input/output interface between the blocks. Accordingly, in order to establish connection between the blocks, a technology for accommodating such difference of the bus width or the input/output interface is needed.
As an interface circuit accommodating difference of the interface, a bridge circuit disclosed in Japanese Patent Application Laid-Open No. 2000-311132 is employed, for example.
As shown in FIG. 39, a bus connection circuit employing the bridge circuit has a first bus 1001 including a 64 bit data line and a control command line, a second bus 1002 including a 32 bit data line and a control command line, a bus bridge circuit 1003 connected between the bus 1001 and the bus 1002, bus master units 1004 and 1005 having 64 bit data line connected to the first bus 1001, bus slave units 1006 and 1007 having 64 bit data line, bus master units 1008 and 1009 having 32 bit data line connected to the second bus 1002, bus slave units 1010 and 1011 having 32 bit data line, an arbitration circuit 1012 on the side of the first bus 1001 and an arbitration circuit 1013 on the side of the second bus 1002.
Operation of the conventional bus connection circuit will be discussed hereinafter with reference to FIG. 39.
It should be noted that while there are non-split transfer continuously performing command transfer and data transfer and split transfer performing command transfer and data transfer discontinuously as data transfer system, discussion will be given hereinafter in terms of split transfer.
The bus master unit 1004 is responsive to a read command or address output from an external master unit (not shown), such as CPU and so forth, to output an arbitration request signal to the arbitration circuit 1012 in order to obtain bus right. The arbitration circuit 1012 performs arbitration and thereafter provides bus right of the first bus 1001 to the bus master unit 1004 by outputting an arbitration grant signal.
The bus master unit 1004 obtaining the bus right outputs the read command, address and device ID (number uniquely assigned for each connected master) to the first bus 1001 via the control command line to release the bus right.
The bus bridge circuit 1003 receives read command, address and device ID output from the first bus 1001 for detecting that the read command is for the bus slave unit 1011 based on address. Since the bus slave unit 1011 is connected to the second bus 1002, the bus bridge circuit 1003 outputs the arbitration request signal to the arbitration circuit 1013 in order to obtain bus right for the second bus 1002. The arbitration circuit 1013 provides bus right for the second bus 1002 to the bus bridge circuit 1003 by outputting an arbitration grant signal after arbitration.
The bus bridge circuit 1003 obtaining the bus right outputs read command, address and device ID to the second bus 1002 to release the bus right for the second bus 1002.
The bus slave unit 1011 detects that the address indicates own unit, receives the read command and transfers the read command to the external slave unit (not shown) connected to the bus slave unit 1011. The external slave unit receiving the read command performs process on the basis of read command to output read data to the bus slave unit 1011.
The bus slave unit 1011 receiving the read data outputs an arbitration request signal to the arbitration circuit 1013 in order to obtain bus right for the second bus 1002. The arbitration circuit 1013 provides bus right for the second bus 1002 to the bus slave unit 1011 by outputting the arbitration grant signal after performing arbitration.
The bus slave unit 1011 obtaining the bus right outputs read data and device ID to the second bus 1002 to release bus right for the second bus 1002. The bus bridge circuit 1003 detects data output to the bus master unit 1004 on the basis of device ID output to the second bus 1002. The arbitration circuit 1012 performs arbitration to provide bus right for the first bus 1001 by outputting the arbitration grant signal.
The bus bridge circuit 1003 obtaining the bus right converts received read data of 32 bit width into data of 64 bit width to release bus right for the first bus 1001 by outputting the converted data together with device ID to the first bus.
Since device ID on the first bus 1001 matches with own device ID, the bus master unit 1004 takes read data on the first bus 1001 and outputs taken data to the external master unit.
Thus, non-split transfer based on read command is executed.
In case of split transfer based on write command, operation is performed as follows.
The bus master unit 1004 releases bus right for the first bus 1001 by outputting write command, address and write data.
The bus bridge circuit 1003 receives 64 bit write data converts 64 bit write data into 32 bit write data after obtaining bus right for the second bus 1002 and releases bus right of the second bus 1002 by outputting converted 32 bit write data together with write command and address to the second bus 1002.
The bus slave unit 1011 receives the write command and write data for transferring to the external slave unit. The external slave unit performs writing operation of the write data on the basis of the write command.
In case of non-split transfer, since the bus slave units 1006, 1007, 1010 and 1011 are not required to obtain bus right, discussion will be given as an arbitration request line and an arbitration grant line are not present between each bus slave unit and arbitration circuits 1012 and 1013 in FIG. 39.
In case of the non-split transfer based on read command, releasing of bus right for the first bus 1001 by the bus master unit 1004 is not performed until reception of read data from the bus slave unit 1011. Also, releasing of bus right for the second bus 1002 by the bus bridge circuit 1003 is not performed until reception of read data from bus slave unit.
On the other hand, non-split transfer based on the write command is substantially the same as split transfer except that the bus right for the first bus is not released after outputting write data, write command and address to the first bus 1001. Therefore, discussion will be eliminated in order to keep the disclosure simple enough by avoiding redundant disclosure and to facilitate clear understanding of the present invention.
As set forth above, number of times to obtain bus right and number of times requiring arbitration by arbitration circuit is four times in split transfer, twice in non-split transfer, and twice in both transfer in case of execution of the write command.
Normally, in arbitration operation in one time, approximately at least four clocks are required. Therefore, eight to sixteen clocks are required for arbitration operation.
As set forth above, in the conventional bus connection circuit, since a period required for arbitration operation is long for many times of arbitration to perform data transfer between buses in the bus bridge circuit, bus performance can be lowered.
Furthermore, upon execution of the write command, the bus master unit can terminate bus cycle by releasing bus right for the first bus before completion of transfer of write data to the slave side, it is feared that write data transmitted upon occurrence of transfer error is lost. Therefore, an extra circuit is required for sending notice of transfer error to the bus master unit.
On the other hand, for notifying transfer error to the bus master unit, it becomes necessary to perform notice after the bus bridge circuit obtains bus right for the first bus through arbitration by the arbitration circuit. Therefore, number of times of arbitration is further increased upon occurrence of the transfer error to lower throughput of the bus. It should be noted that loss of write data upon occurrence of transfer error can be avoided if bus right for the first bus is not released. However, since the first bus can be occupied until completion of bus cycle, use efficiency of bus can be lowered.
Also, in the conventional bus connection circuit, each bus bridge circuit 1003 is required to incorporate bus control circuit adapted to the bus master unit and bus slave unit in the first bus and the second bus.
Accordingly, in the conventional bus control circuit set forth above, the bus bridge circuit requires four control circuits, i.e. a bus master control circuit for the first bus, a bus master control circuit for the second bus, a bus slave control circuit for the first bus and a bus slave control circuit for the second bus. Thus, scale of circuit of the bus bridge circuit is inherently increased according to increasing of number of buses connected to the bus bridge circuit.